201807 – Moore – Signal Design Verification – A Systems Engineering Approach

There are many signalling projects undertaken each year in Australasia. Each project involves the signalling design being produced by a signalling designer or team of signalling designers. The objective is to produce a design that achieves a set of requirements for the operating railway. There is the possibility of Human Error in the undertaking of the design. There is a statutory requirement to ensure that the signalling design is safe So Far As Is Reasonably Practical (SFAIRP).

To achieve the project requirements in a safe manner, a great majority of projects knowingly or not apply the V design development cycle. As part of this development process a verification of the design is undertaken.

This paper examines why we undertake the design verification, how we undertake the design verification and the outputs from the verification process. The paper also examines the scope of the verification process.

The design and verification activities are also reviewed in the context of the Systems Engineering Life Cycle.